Originally Posted by
wisnon 
Wow, what interesting talk about i2s and Signal integrity. Let's see this dates back to...Aug, 2013!
that cant be right now, can it?
Q&A with John Swenson. Part 2: Are Bits Just Bits?
Next let’s look at the other inputs to the DAC chip,
such as the I2S signals. Those signals might have quite a bit of jitter
depending on where they come from. Even though the main clock is supposed to be the arbiter of timing, these other inputs can also affect the internal timing. Each one of those signals has a return current back to wherever it came from, creating ground plane noise to the DAC chip. They also create noise on the internal chip traces from the transistors receiving those signals. All of this creates noise the chip sees whose spectrum is related to the spectrum of the jitter on the I2S signals. So not only is jitter on the master clock important, but so is jitter on the I2S signals. This is important to realize,
jitter on ALL input signals to the DAC chip can modify the timing internal to the chip.
So in order to fix this jitter on the I2S signals we “reclock” them with a flip flop clocked by the master clock. BUT the signals going into the flop also cause ground plane noise with a spectrum related to the jitter on the inputs, AND some of the transistors inside the flop are also switching based on the input signals, adding to the ground plane noise correlated to the “jittery” inputs. So why bother reclocking? It DOES decrease jitter, it just doesn’t eliminate it. If the I2S signals have quite a bit of jitter, the reclocking can cut it down by quite a bit, but there is STILL jitter on the output that is correlated to the input jitter AND there is noise on the ground plane related to the input signals that can influence the clock, clock mux, and DAC chip. So while reclocking can help, it is not a panacea.
So now the crux of the matter, how can what goes into the USB receiver affect any of this? In several ways: packet jitter, edge jitter, PLLs. I’ll go over each of these.
Packet jitter is the difference in the arrival time of packets to the receiver chip. USB packets are transmitted over the bus at either 1000 per second (full speed mode) or 8000 per second (high speed mode). Every time one of those packets hits the receiver a lot of activity happens inside the receiver chip.
